Asic Architect

ASIC Architect's high performance cores come in multiple datapath flavors with the choice of 8-bit or 16-bit PIPE PHY Interface. The cores have been architected to achieve very low latency, high throughput, and quick timing closure with a very tiny silicon footprint. The consumer interface supplies practical and integration-friendly mechanisms for the integration of the cores to the consumer logic. Please refer to the product matrix below to choose the core for your ASIC/FPGA.